1. FIELD OF THE INVENTION
This invention relates to integrated circuit structures and in particular, to a method for fabricating multiple isolation regions in such structures resulting in devices having high yield due to less defects and improved device topography.
2. DESCRIPTION OF THE PRIOR ART
Numerous techniques are known for providing electrical isolation of discrete devices in an integrated circuit structure. Junction isolation and oxide isolation are two such techniques. The two primary goals of these isolation methods have been to reduce the size of the isolation regions in proportion to the total area of silicon available for formation of active devices and to decrease the size of the active devices. However, certain known disadvantages are related to the use of either junction isolation or oxide isolation in manufacturing integrated circuits. It is recognized, for example, that the use of diffused regions for junction isolation results in larger, less well defined circuits than desired for many applications. The use of junction isolation, therefore, has been largely replaced by the use of oxide isolation techniques.
Oxide isolation, however, also suffers from certain known disadvantages (see, e.g. VORA et al., U.S. Pat. No. 4,374,011), including a problem known as "birds beak" or encroachment, in which regions of oxidized semiconductor material will slope into adjoining regions of semiconductor material. Encroachment is undesirable because it uses additional amounts of the surface of the integrated circuit structure. Furthermore, oxidized semiconductor material formed using conventional techniques protrudes upwards from the surface of the surrounding material. The non-planar upper surface which results can cause problems with subsequently formed conducting or insulating layers which could have a propensity to crack where they cross the upward projections. In addition, excess stresses resulting from long oxidation periods can cause dislocation defects which seriously affect production yield.
A further disadvantage is that the fullest capabilities of state-of-the-art processing techniques cannot be utilized in fabricating devices employing conventional isolation methods. The use of diffused junction isolation, for example, limits the feature size and density benefits that can be gained from stepper lithography and plasma etching processing techniques. In this case, the isolation method itself defines a minimum feature size which is larger than the feature size that is otherwise achievable with stepper lithography and plasma etching.
The aforementioned disadvantages become increasingly troublesome as integrated circuit device geometries are reduced for Very Large Scale Integration (VLSI) applications. It would be desirable, therefore, to develop a method for fabricating integrated circuits employing device isolation methods which overcome the planarity and scaling limitation problems of conventional prior art fabrication techniques and which allow the maximum shrinking of device geometries through the use of state-of-the-art processing techniques.